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low power jfet-input op amps ada4062-2/ada4062-4 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2010 analog devices, inc. all rights reserved. features low input bias current: 50 pa maximum offset voltage 1.5 mv maximum for b grade (ada4062-2 soic package) 2.5 mv maximum for a grade offset voltage drift: 5 v/c typical slew rate: 3.3 v/s typical cmrr: 90 db typical low supply current: 165 a typical high input impedance unity-gain stable 5 v to 15 v dual-supply operation packaging 8-lead soic, 8-lead msop, 10-lead lfcsp, 14-lead tssop, and 16-lead lfcsp packages applications power controls and monitoring active filters industrial/process controls body probe electronics data acquisition integrators input buffering general description the ada4062-2 and ada4062-4 are dual and quad jfet-input amplifiers with industry-leading performance. they offer lower power, offset voltage, drift, and ultralow bias current. the ada4062-2 b grade (soic package) features a typical low offset voltage of 0.5 mv, an offset drift of 5 v/c, and a bias current of 2 pa. the ada4062 family is ideal for various applications, including process controls, industrial and instrumentation equipment, active filtering, data conversion, buffering, and power control and monitoring. with a low supply current of 165 a per amplifier, they are well suited for lower power applications. the ada4062 family is also specified for the extended industrial temperature range of ?40c to +125c. the ada4062-2 is available in lead-free, 8-lead soic, 8-lead msop, and 10-lead lfcsp (1.6 mm 1.3 mm 0.55 mm) packages, while the ada4062-4 is available in lead-free, 14-lead tssop and 16-lead lfcsp packages. pin configurations out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4062-2 top view (not to scale) 07670-001 figure 1. 8-lead narrow-body soic and 8-lead msop 7 8 3 2 5 6 4 nc +in b v? ?i n a +in a out b ?in b n c = no connect 07670-065 10 9 1 nc v+ out a top view (not to scale) ada4062-2 figure 2. 10-lead lfcsp ada4062-4 1 2 3 4 5 6 7 ?in a +in a v+ out b ?in b +in b out a 14 13 12 11 10 9 8 ?in d +in d v? out c ?in c +in c out d top view (not to scale) 07670-064 figure 3. 14-lead tssop 07670-068 notes 1. nc = no connect. 2 . it is recommended to connect the exposed pad to v?. ada4062-4 top view (not to scale) ?in a +in a v+ +in b ?in d +in d v? +in c ?in b out b out c ?in c nc out a out d nc 12 11 10 1 3 4 9 2 6 5 7 8 16 15 14 13 figure 4. 16-lead lfcsp table 1. low power op amps precision cmos precision high bandwidth high bandwidth single ad8663 ad8641 dual ad8667 ad8642 ad8682 quad ad8669 ad8643 ad8684
ada4062-2/ada4062-4 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? pin configurations ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics ............................................................. 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? power sequencing ........................................................................ 5 ? esd caution...................................................................................5 ? typical performance characteristics ..............................................6 ? applications information .............................................................. 15 ? notch filter ................................................................................. 15 ? high-side signal conditioning ................................................ 15 ? micropower instrumentation amplifier ................................. 15 ? phase reversal ............................................................................ 16 ? schematic ......................................................................................... 17 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 20 ? revision history 2 /10rev. a to rev. b added 16-lead lfcsp package........................................ universal changes to features section, general description section, and table 1 ................................................................................................ 1 changes to offset voltage drift parameter, table 2 .................... 3 changes to table 4 ............................................................................ 5 changes to typical performance characteristics layout ............ 6 added figure 6 and figure 9; renumbered sequentially ........... 6 changes to figure 7, figure 8, and figure 10 ............................... 6 changes to figure 25 and figure 28 ............................................... 9 changes to figure 37 and figure 40 ............................................. 11 changes to figure 41 to figure 46 ................................................ 12 changes to figure 47 and figure 50 ............................................. 13 changes to figure 53 to figure 58 ................................................ 14 changes to notch filter section and micropower instrumentation amplifier section ............................................................................ 15 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 20 7/09rev. 0 to rev. a added ada4062-4 ............................................................. universal added 14-lead tssop package ....................................... universal added 10-lead lfcsp package ....................................... universal changes to features section and table 1 ....................................... 1 changes to table 2 ............................................................................. 3 changes to thermal resistance section ........................................ 5 changes to figure 5, figure 6, figure 8, and figure 9 .................. 6 changes to figure 37 and figure 40............................................. 11 changes to figure 41 and figure 44............................................. 12 changes to figure 47, figure 48, figure 50, and figure 51....... 13 added figure 49 and figure 52; renumbered sequentially ..... 13 changes to figure 57 and figure 59............................................. 15 changes to phase reversal section and figure 61 ..................... 16 changes to figure 63 ...................................................................... 17 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19 10/08revision 0: initial version
ada4062-2/ada4062-4 rev. b | page 3 of 20 specifications electrical characteristics v sy = 15 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage v os b grade (ada4062-2, 8-lead soic only) 0.5 1.5 mv ?40c t a +125c 3 mv a grade 0.75 2.5 mv ?40c t a +125c 5 mv offset voltage drift ?v os /?t ?40c t a +125c 5 v/c input bias current i b 2 50 pa ?40c t a +125c 5 na input offset current i os 0.5 25 pa ?40c t a +125c 2.5 na input voltage range ?40c t a +125c ?11.5 +15 v common-mode rejection ratio cmrr b grade (ada4062-2, 8-lead soic only) v cm = ?11.5 v to +11.5 v 80 90 db ?40c t a +125c 80 db a grade v cm = ?11.5 v to +11.5 v 73 90 db ?40c t a +125c 70 db large-signal voltage gain a vo r l = 10 k, v o = ?10 v to +10 v 76 83 db ?40c t a +125c 72 db input resistance r in 10 t input capacitance, differential mode c indm 1.5 pf input capacitance, common mode c incm 4.8 pf output characteristics output voltage high v oh r l = 10 k to v cm 13 13.5 v ?40c t a +125c 12.5 v output voltage low v ol r l = 10 k to v cm ?13.8 ?13 v ?40c t a +125c ?12.5 v short-circuit current i sc 20 ma closed-loop output impedance z out f = 1 khz, a v = 1 1 power supply power supply rejection ratio psrr b grade (ada4062-2, 8-lead soic only) v sy = 4 v to 18 v 80 90 db ?40c t a +125c 80 db a grade v sy = 4 v to 18 v 74 90 db ?40c t a +125c 70 db supply current per amplifier i sy i o = 0 ma 165 220 a ?40c t a +125c 260 a dynamic performance slew rate sr r l = 10 k, c l = 100 pf, a v = 1 3.3 v/s settling time t s to 0.1%, v in = 10 v step, c l = 100 pf, r l = 10 k, a v = 1 3.5 s gain bandwidth product gbp r l = 10 k, a v = 1 1.4 mhz phase margin m r l = 10 k, a v = 1 78 degrees channel separation (ada4062-2 only) cs f = 1 khz 135 db channel separation (ada4062-4 only) cs f = 1 khz 130 db
ada4062-2/ada4062-4 rev. b | page 4 of 20 parameter symbol conditions min typ max unit noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 1.5 v p-p voltage noise density e n f = 1 khz 36 nv/hz current noise density i n f = 1 khz 5 fa/hz
ada4062-2/ada4062-4 rev. b | page 5 of 20 absolute maximum ratings thermal resistance table 3. parameter rating supply voltage 18 v input voltage v sy differential input voltage v sy input current 10 ma output short-circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. it was measured using a standard 4-layer board. table 4. thermal resistance package type ja jc unit 8-lead soic 120 45 c/w 8-lead msop 142 45 c/w 10-lead lfcsp 132 46 c/w 14-lead tssop 112 35 c/w 16-lead lfcsp 75 12 c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power sequencing the supply voltages of the op amps must be established simultaneously with, or before, any input signals are applied. if this is not possible, the input current must be limited to 10 ma. esd caution
ada4062-2/ada4062-4 rev. b | page 6 of 20 typical performance characteristics t a = 25c, unless otherwise noted. 0 10 20 30 40 50 60 70 ?4 ?3 ?2 ?1 0 1 2 4 3 07670-054 v os (mv) number of amplifers v sy = 5v v cm = 0v based on 600 op amps figure 5. input offset voltage distribution 0 10 20 30 40 ?20246810 07670-055 tcv os (v/c) number of amplifers ada4062-2 only v sy = 5v ?40c t a +125c based on 200 op amps figure 6. input offset voltage drift distribution 07670-070 0 0 5 10 15 20 25 2 4 6 8 10 12 14 16 tcv os (v/c) number of amplifiers 18 ada4062-4 only v sy = 5v ?40c t 125c based on 200 op amps figure 7. input offset voltage drift distribution 0 40 80 120 160 200 240 280 ?4 ?3 ?2 ?1 0 1 2 4 3 07670-003 v os (mv) number of amplifers v sy = 15v v cm = 0v based on 600 op amps figure 8. input offset voltage distribution 0 10 20 30 40 ?2 0 2 4 6 8 10 07670-005 tcv os (v/c) number of amplifers ada4062-2 only v sy = 15v ?40c t a +125c based on 200 op amps figure 9. input offset voltage drift distribution 07670-069 0 5 10 15 20 25 tcv os (v/c) number of amplifiers 0 2 4 6 8 1012141618 ada4062-4 only v sy = 15v ?40c t 125c based on 200 op amps figure 10. input offset voltage drift distribution
ada4062-2/ada4062-4 rev. b | page 7 of 20 ?4 ?3 ?2 ?1 0 1 2 3 4 5 07670-056 v cm (v) v sy = 5v ?5 ?3 ?1 ?2 ?4 1 3 0 5 2 4 v os (mv) figure 11. input offset voltage vs. common-mode voltage 0.1 1 10 100 1000 10000 ?50 ?25 0 25 50 75 100 125 07670-012 temperature (c) i b (pa) v sy = 5v figure 12. input bias current vs. temperature ?2 ?1 0 1 2 3 ?3?2?1012345 07670-013 v cm (v) i b (pa) v sy = 5v figure 13. input bias current vs. common-mode voltage ?5 ?3 ?1 ?2 ?4 1 3 0 5 2 4 ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 15 07670-006 v cm (v) v os (mv) v sy = 15v figure 14. input offset voltage vs. common-mode voltage 0.1 1 10 100 1000 10000 ?50 ?25 0 25 50 75 100 125 07670-009 temperature (c) i b (pa) v sy = 15v figure 15. input bias current vs. temperature 0 1 2 3 4 5 ?12?10?8?6?4?2 0 2 4 6 810121416 07670-010 v cm (v) i b (pa) v sy = 15v figure 16. input bias current vs. common-mode voltage
ada4062-2/ada4062-4 rev. b | page 8 of 20 0.1 1 10 0.01 0.1 1 10 100 v+ ? v oh v ol ? v? 07670-014 load current (ma) output voltage to supply rail (v) v sy = 5v figure 17. output voltage to supply rail vs. load current 0 220 200 180 160 140 120 100 80 60 40 20 0 2 4 6 8 1012141618 07670-146 supply voltage (v) supply current/amp (a) ?40c +25c +85c +125c figure 18. supply current/amp vs. supply voltage 0 0.5 1.0 1.5 2.0 07670-018 temperature (c) output votlage to supply rail (v) v ol ? v? v+ ? v oh v sy = 5v r l = 10k ? ?50 ?25 125 0 25 50 75 100 figure 19. output voltage to supply rail vs. temperature 0.1 1 10 0.01 0.1 1 10 100 v+ ? v oh v ol ? v? 07670-011 load current (ma) output voltage to supply rail (v) v sy = 15v figure 20. output voltage to supply rail vs. load current 100 200 190 180 170 160 150 140 130 120 110 ?50 ?25 0 25 50 75 100 125 150 07670-149 temperature (c) supply current/amp (a) v sy = 15v v sy = 5v figure 21. supply current/amp vs. temperature 0 0.5 1.0 1.5 2.0 ?50 ?25 125 0 25 50 75 100 07670-015 temperature (c) output votlage to supply rail (v) v+ ? v oh v ol ? v? v sy = 15v r l = 10k ? figure 22. output voltage to supply rail vs. temperature
ada4062-2/ada4062-4 rev. b | page 9 of 20 ?60 ?40 ?20 0 20 40 60 80 100 120 1k 10k 100k 1m 10m 100m ?60 ?40 ?20 0 20 40 60 80 100 120 phase (degrees) 07670-019 frequency (hz) gain (db) v sy = 5v phase gain figure 23. open-loop gain and phase vs. frequency 50 40 30 20 10 0 ?10 ?20 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) v sy = 5v a v = +100 a v = +10 a v = +1 07670-020 figure 24. closed-loop gain vs. frequency 0.1 10 1000 1 100 100 1k 10k 100k 1m 10m a v = +1 07670-021 frequency (hz) z out ( ? ) a v = +10 a v = +100 v sy = 5v figure 25. output impe dance vs. frequency ?60 ?40 ?20 0 20 40 60 80 100 120 1k 10k 100k 1m 10m 100m ?60 ?40 ?20 0 20 40 60 80 100 120 phase (degrees) 07670-016 frequency (hz) gain (db) v sy = 15v phase gain figure 26. open-loop gain and phase vs. frequency 50 40 30 20 10 0 ?10 ?20 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) v sy = 15v a v = +100 a v = +10 a v = +1 07670-017 figure 27. closed-loop gain vs. frequency 100 1k 10k 100k 1m 10m a v = +1 a v = +10 a v = +100 v sy = 15v 07670-018 frequency (hz) z out ( ? ) 0.1 10 1000 1 100 figure 28. output impe dance vs. frequency
ada4062-2/ada4062-4 rev. b | page 10 of 20 100 80 90 70 60 50 40 30 20 10 0 100 1k 10k 100k 1m 10m cmrr (db) frequency (hz) v sy = 5v 07670-025 figure 29. cmrr vs. frequency psrr? ?20 0 20 40 60 80 100 120 10 100 psrr+ v sy = 5v 1k 10k 100k 1m 10m 07670-026 frequency (hz) psrr (db) figure 30. psrr vs. frequency 0 10 20 30 40 50 60 10 100 1000 10000 v sy = 5v a v = +1 r l = 10k ? 07670-030 c l (pf) overshoot (%) figure 31. small-signal overshoot vs. load capacitance 100 80 90 70 60 50 40 30 20 10 0 100 1k 10k 100k 1m 10m cmrr (db) frequency (hz) v sy = 15v 07670-022 figure 32. cmrr vs. frequency psrr? ?20 0 20 40 60 80 100 120 140 10 100 psrr+ v sy = 15v 1k 10k 100k 1m 10m 07670-023 frequency (hz) psrr (db) figure 33. psrr vs. frequency 0 10 20 30 40 50 60 10 100 1000 10000 v sy = 15v a v = +1 r l = 10k ? 07670-027 c l (pf) overshoot (%) figure 34. small-signal overshoot vs. load capacitance
ada4062-2/ada4062-4 rev. b | page 11 of 20 v sy = 5v v in = 4v p-p a v = +1 r l = 10k ? c l = 100pf 07670-031 time (4s/div) voltage (1v/div) figure 35. large-signal transient response 07670-032 time (10s/div) voltage (20mv/div) v sy = 5v v in = 100mv p-p a v = +1 r l = 10k ? c l = 100pf figure 36. small-signal transient response ?6 ?4 ?2 0 0 4 2 input output output voltage (v) 07670-036 input voltage (v) v sy = 5v a v =?10 time (2s/div) figure 37. negative overload recovery v sy = 15v v in = 20v p-p a v = +1 r l = 10k ? c l = 100pf 07670-028 time (10s/div) voltage (5v/div) figure 38. large-signal transient response 07670-029 time (10s/div) voltage (20mv/div) v sy = 15v v in = 100mv p-p a v = +1 r l = 10k ? c l = 100pf figure 39. small-signal transient response 0 2 4 ?20 ?15 ?10 ?5 0 input output output voltage (v) 07670-033 input voltage (v) time (2s/div) v sy = 15v a v =?10 figure 40. negative overload recovery
ada4062-2/ada4062-4 rev. b | page 12 of 20 ?2 0 2 4 2 0 ?2 input output output voltage (v) 07670-037 input voltage (v) time (2s/div) v sy = 5v a v =?10 figure 41. positive overload recovery 07670-075 time (2s/div) voltage (1v/div) +20mv ?20mv 0v input output error band v sy = 5v c l = 100pf r l = 10k ? figure 42. positive settling time to 0.1% 07670-076 time (2s/div) voltage (1v/div) +20mv ?20mv 0v input output error band v sy = 5v c l = 100pf r l = 10k ? figure 43. negative settling time to 0.1% ?5 0 5 10 15 ?2 0 2 input output output voltage (v) 07670-034 input voltage (v) time (2s/div) v sy = 15v a v =?10 figure 44. positive overload recovery 07670-077 time (2s/div) voltage (5v/div) +100mv ?100mv 0v input output error band v sy = 15v c l = 100pf r l = 10k ? figure 45. positive settling time to 0.1% 07670-078 time (2s/div) voltage (5v/div) +100mv ?100mv 0v input output error band v sy = 15v c l = 100pf r l = 10k ? figure 46. negative settling time to 0.1%
ada4062-2/ada4062-4 rev. b | page 13 of 20 07670-043 frequency (hz) voltage noise density (nv/ hz) 10 100 1000 11 01 0 0 1 k v sy = 5v figure 47. voltage noise density 07670-044 time (1s/div) input noise voltage (0.5v/div) v sy = 5v figure 48. 0.1 hz to 10 hz noise ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k v sy = 5v v in = 5v p-p r l = 10k ? ada4062-2 only 07670-049 frequency (hz) channel separation (db) r l 100k ? 1k? figure 49. channel separation vs. frequency (ada4062-2 only) 07670-040 frequency (hz) voltage noise density (nv/ hz) 10 100 1000 11 01 0 0 1 k v sy = 15v figure 50. voltage noise density 07670-041 time (1s/div) input noise voltage (0.5v/div) v sy = 15v figure 51. 0.1 hz to 10 hz noise ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 07670-046 frequency (hz) channel separation (db) v sy = 15v v in = 10v p-p r l = 10k ? ada4062-2 only r l 100k ? 1k? figure 52. channel separation vs. frequency (ada4062-2 only)
ada4062-2/ada4062-4 rev. b | page 14 of 20 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k v sy = 5v v in = 5v p-p r l = 10k ? ada4062-4 only 07670-067 frequency (hz) channel separation (db) r l 100k ? 1k? figure 53. channel separation vs. frequency (ada4062-4 only) 07670-071 thd + n (%) 100 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1 10 amplitude (v rms) v s = 5v f = 1khz r l = 10k ? figure 54. thd + n vs. amplitude 07670-073 thd + n (%) 1 0.1 0.01 0.001 10 100 1k 10k 100k frequency (hz) v sy = 5v v in = 0.5v rms r l = 10k ? figure 55. thd + n vs. frequency ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 07670-066 frequency (hz) channel separation (db) v sy = 15v v in = 10v p-p r l = 10k ? ada4062-4 only r l 100k ? 1k? figure 56. channel separation vs. frequency (ada4062-4 only) 07670-072 thd + n (%) 10 0.1 1 0.01 0.001 0.001 0.01 0.1 1 10 amplitude (v rms) v s = 15v f = 1khz r l = 10k ? figure 57 thd + n vs. amplitude 0 7670-074 thd + n (%) 1 0.01 0.1 0.001 100 1k 10k 100k 1m frequency (hz) v s = 15v v in = 2v rms r l = 10k ? figure 58. thd + n vs. frequency
ada4062-2/ada4062-4 rev. b | page 15 of 20 applications information notch filter a notch filter rejects a specific interfering frequency and can be implemented using a single op amp. figure 59 shows a 60 hz notch filter that uses the twin-t network with the ada4062-x configured as a voltage follower. the ada4062-x works as a buffer that provides high input resistance and low output impedance. the low bias current (2 pa typical) and high input resistance (10 t typical) of the ada4062-x enable large resistors and small capacitors to be used. alternatively, different combinations of resistor and capacitor values can be used to achieve the desired notch frequency. however, the major drawback to this circuit topology is the need to ensure that all the resistors and capacitors be closely matched. if they are not closely matched, the notch frequency offset and drift cause the circuit to attenuate at a frequency other than the ideal notch frequency. therefore, to achieve the desired performance, 1% or better component tolerances are usually required. in addition, a notch filter requires an op amp with a bandwidth of at least 100 to 200 the center frequency. hence, using the ada4062-x with a bandwidth of 1.4 mhz is excellent for a 60 hz notch filter. figure 60 shows the frequency response of the notch filter. at 60 hz, the notch filter has about 50 db attenuation of signal. +v sy ?v sy in v o f o = r1 = r2 = 2r3 c1 = c2 = 07670-060 r1 804k ? r2 804k ? r3 402k ? c3 6.6nf c2 3.3nf c3 2 c1 3.3nf ada4062-x 1 2 r 1 c 1 figure 59. notch filter circuit 07670-057 frequency (hz) gain (db) 20 10 0 ?10 ?30 ?20 ?40 ?50 ?60 ?70 ?80 10 100 1k figure 60. frequency response of the notch filter high-side signal conditioning many applications require the sensing of signals near the positive rail. the ada4062-x can be used in high-side current sensing applications. figure 61 shows a high-side signal conditioning circuit using the ada4062-x. the ada4062-x has an input common-mode range that includes the positive supply (?11.5 v v cm +15 v). in the circuit, the voltage drop across a low value resistor, such as the 0.1 shown in figure 61 , is amplified by a factor of 5 using the ada4062-x. ada4062-x +15 v +15v ?15v 100k ? 0.1 ? 100k ? 500k ? 500k ? v o r l 07670-058 figure 61. high-side signal conditioning micropower instrumentation amplifier the ada4062-2 is a dual amplifier and is perfectly suited for applications that require lower supply currents. for supply voltages of 15 v, the supply current per amplifier is 165 a typical. the ada4062-2 also offers a typical low offset voltage drift of 5 v/c and a very low bias current of 2 pa, which make it well suited for instrumentation amplifiers. figure 62 shows the classic 2-op-amp instrumentation amplifier with four resistors using the ada4062-2. the key to high cmrr for this instrumentation amplifier are resistors that are well matched to both the resistive ratio and relative drift. for true difference amplification, matching of the resistor ratio is very important, where r3/r4 = r1/r2. assuming perfectly matched resistors, the gain of the circuit is 1 + r2/r1, which is approximately 100. tighter matching of two op amps in one package, as is the case with the ada4062-2, offers a significant boost in performance over the classical 3-op-amp configuration. overall, the circuit only requires about 330 a of supply current. r3 10.1k ? r4 1m ? +15v 1/2 ?15v v1 r2 1m ? +15v ?15v v2 r1 10.1k ? ada4062-2 ada4062-2 v o v o = 100(v2 ? v1) typical: 0.5mv < v2 ? v1 < 135mv typical: ?13.8v < v o < +13.5v use matched resistors 07670-059 1/2 figure 62. micropower instrumentation amplifier
ada4062-2/ada4062-4 rev. b | page 16 of 20 phase reversal phase reversal occurs in some amplifiers when the input common- mode voltage range is exceeded. when the voltage driving the input to these amplifiers exceeds the maximum input common- mode voltage range, the output of the amplifiers changes polarity. most jfet input amplifiers have phase reversal if either input exceeds the input common-mode range. for the ada4062-x, the output does not phase reverse if one or both of the inputs exceeds the input voltage range but remains within the positive supply rail and 0.5 v above the negative supply rail. in other words, for an application with a supply voltage of 15 v, the input voltage can be as high as +15 v without any output phase reversal. however, when the voltage of the inputs is driven beyond ?14.5 v, phase reversal occurs due to saturation of the input stage leading to forward biasing of the gate-drain diode. phase reversal in ada4062-x can be prevented by using a schottky diode to clamp the input terminals to each other. in the simple buffer circuit in figure 63 , d1 protects the op amp against phase reversal, and r limits the input current that flows into the op amp. +v sy ?v sy v o 07670-053 r 10k ? ada4062-x d1 in5711 figure 63. phase reversal solution circuit 07670-063 time (40 s/div) vol t age (5v/div) v sy = 15v v out v in figure 64. no phase reversal
ada4062-2/ada4062-4 rev. b | page 17 of 20 schematic 07670-062 ? in v? v + out +in figure 65. simplified schematic of the ada4062-x
ada4062-2/ada4062-4 rev. b | page 18 of 20 outline dimensions compliant to jedec standards mo-187-aa 100709-b 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 66. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 67. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) 033007-a 0.40 bsc 1 46 9 p i n 1 i d e n t i f i e r top view bottom view seating plane 0.20 dia typ 0.60 0.55 0.50 0.20 bsc 1.60 1.30 0.55 0.40 0.30 0.35 0.30 0.25 0.05 max 0.02 nom figure 68. 10-lead lead frame chip scale package [lfcsp_uq] 1.30 mm 1.60 mm, body, ultra thin quad (cp-10-10) dimensions shown in millimeters
ada4062-2/ada4062-4 rev. b | page 19 of 20 compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 69. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 01-13-2010-d 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. figure 70. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters
ada4062-2/ada4062-4 rev. b | page 20 of 20 ordering guide model 1 temperature range package description package option branding ada4062-2armz ?40c to +125c 8-lead msop rm-8 a25 ada4062-2armz-rl ?40c to +125c 8-lead msop rm-8 a25 ada4062-2armz-rl7 ?40c to +125c 8-lead msop rm-8 a25 ada4062-2arz ?40c to +125c 8-lead soic_n r-8 ada4062-2arz-r7 ?40c to +125c 8-lead soic_n r-8 ada4062-2arz-rl ?40c to +125c 8-lead soic_n r-8 ada4062-2brz ?40c to +125c 8-lead soic_n r-8 ada4062-2brz-r7 ?40c to +125c 8-lead soic_n r-8 ada4062-2brz-rl ?40c to +125c 8-lead soic_n r-8 ada4062-2acpz-r2 ?40c to +125c 10-lead lfcsp_uq cp-10-10 j ada4062-2acpz-rl ?40c to +125c 10-lead lfcsp_uq cp-10-10 j ada4062-2acpz-r7 ?40c to +125c 10-lead lfcsp_uq cp-10-10 j ADA4062-4ARUZ ?40c to +125c 14-lead tssop ru-14 ADA4062-4ARUZ-rl ?40c to +125c 14-lead tssop ru-14 ada4062-4acpz-r2 ?40c to +125c 16-lead lfcsp_wq cp-16-22 a2k ada4062-4acpz-r7 ?40c to +125c 16-lead lfcsp_wq cp-16-22 a2k ada4062-4acpz-rl ?40c to +125c 16-lead lfcsp_wq cp-16-22 a2k 1 z = rohs compliant part. ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07670-0-2 /10(b)

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